1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to thermal management structures for stacked semiconductor chips and to methods of assembling the same.
2. Description of the Related Art
Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Another critical design issue associated with stacked semiconductor chips is thermal management. Most electrical devices dissipate heat as a result of resistive losses, and semiconductor chips and the circuit boards that carry them are no exception. Still another technical challenge associated with stacked semiconductor chips is testing.
A process flow to transform a bare semiconductor wafer into a collection of chips and then mount those chips on packages or other boards involves a large number of individual steps. Because the processing and mounting of a semiconductor chip proceeds in a generally linear fashion, that is, various steps are usually performed in a specific order, it is desirable to be able to identify defective parts as early in a flow as possible. In this way, defective parts may be identified so that they do not undergo needless additional processing. This economic incentive to identify defective parts as early in the processing phase as possible is certainly present in the design and manufacture of stacked semiconductor chip devices. This follows from the fact that a typical process flow for fabricating a stacked semiconductor chip device includes the multitude of fabrication steps that go into successively mounting a plurality of singulated semiconductor chips to a circuit board. If, for example, the first semiconductor chip mounted to a carrier substrate is revealed to be defective only after several other semiconductor chips are stacked thereon, then all of the material processing steps and the materials associated with the later-mounted chips may have been wasted.
Thermal management of a semiconductor chip or chips in a stacked arrangement remains a technical challenge during required electrical testing of one or more of the semiconductor chips. A given semiconductor chip in a stacked arrangement, whether the first, an intermediary or the last in the particular stack, may dissipate heat to such an extent that active thermal management is necessary in order to either prevent the one or all of the semiconductor chips in the stack from entering thermal runaway or so that one or more of the semiconductor chips in the stack may be electrically tested at near or true operational power levels and frequencies.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.